Project Status (07/28/2016 - 15:53:33) | |||
Project File: | iic_plb_1.xmp | Implementation State: | Programming File Generated |
Module Name: | iic_plb_1 |
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No Errors |
Product Version: | EDK 14.7 |
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122 Warnings (0 new) |
XPS Reports | [-] | ||||
Report Name | Generated | Errors | Warnings | Infos | |
Platgen Log File | 格 7 21 12:40:42 2016 | 0 | 9 Warnings (0 new) | 27 Infos (1 new) | |
Simgen Log File | |||||
BitInit Log File | 岿 7 18 14:36:16 2016 | 0 | 0 | 15 Infos (0 new) | |
System Log File | 格 7 28 15:53:33 2016 |
XPS Synthesis Summary (estimated values) | [-] | |||||
Report | Generated | Flip Flops Used | LUTs Used | BRAMS Used | Errors | |
iic_plb_1 | 格 7 21 12:40:58 2016 | 3991 | 4541 | 20 | 0 | |
iic_plb_1_clock_generator_0_wrapper | 格 7 21 12:40:38 2016 | 0 | ||||
iic_plb_1_lmb_bram_wrapper | 格 7 21 12:40:33 2016 | 16 | 0 | |||
iic_plb_1_ilmb_cntlr_wrapper | 格 7 21 12:40:28 2016 | 2 | 6 | 0 | ||
iic_plb_1_dlmb_cntlr_wrapper | 格 7 21 12:40:22 2016 | 2 | 6 | 0 | ||
iic_plb_1_xps_uartlite_0_wrapper | 荐 7 20 20:27:42 2016 | 155 | 140 | 0 | ||
iic_plb_1_chipscope_plbv46_iba_0_wrapper | 荐 7 20 20:19:49 2016 | 0 | ||||
iic_plb_1_mb_plb_wrapper | 荐 7 20 20:19:39 2016 | 155 | 371 | 0 | ||
iic_plb_1_chipscope_icon_0_wrapper | 配 7 16 13:53:43 2016 | 0 | ||||
iic_plb_1_microblaze_0_wrapper | 拳 7 12 22:38:57 2016 | 2620 | 2980 | 1 | 0 | |
iic_plb_1_proc_sys_reset_0_wrapper | 拳 7 12 21:33:27 2016 | 69 | 54 | 0 | ||
iic_plb_1_xps_iic_0_wrapper | 拳 7 12 17:44:18 2016 | 388 | 492 | 0 | ||
iic_plb_1_mdm_0_wrapper | 拳 7 12 17:44:00 2016 | 123 | 126 | 0 | ||
iic_plb_1_dlmb_wrapper | 拳 7 12 17:43:31 2016 | 1 | 0 | |||
iic_plb_1_ilmb_wrapper | 拳 7 12 17:43:26 2016 | 1 | 0 |
Device Utilization Summary (actual values) | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 3,243 | 11,440 | 28% | ||
Number used as Flip Flops | 3,238 | ||||
Number used as Latches | 1 | ||||
Number used as Latch-thrus | 0 | ||||
Number used as AND/OR logics | 4 | ||||
Number of Slice LUTs | 3,842 | 5,720 | 67% | ||
Number used as logic | 3,439 | 5,720 | 60% | ||
Number using O6 output only | 2,691 | ||||
Number using O5 output only | 85 | ||||
Number using O5 and O6 | 663 | ||||
Number used as ROM | 0 | ||||
Number used as Memory | 257 | 1,440 | 17% | ||
Number used as Dual Port RAM | 64 | ||||
Number using O6 output only | 0 | ||||
Number using O5 output only | 0 | ||||
Number using O5 and O6 | 64 | ||||
Number used as Single Port RAM | 0 | ||||
Number used as Shift Register | 193 | ||||
Number using O6 output only | 70 | ||||
Number using O5 output only | 2 | ||||
Number using O5 and O6 | 121 | ||||
Number used exclusively as route-thrus | 146 | ||||
Number with same-slice register load | 109 | ||||
Number with same-slice carry load | 12 | ||||
Number with other load | 25 | ||||
Number of occupied Slices | 1,400 | 1,430 | 97% | ||
Number of MUXCYs used | 636 | 2,860 | 22% | ||
Number of LUT Flip Flop pairs used | 4,431 | ||||
Number with an unused Flip Flop | 1,465 | 4,431 | 33% | ||
Number with an unused LUT | 589 | 4,431 | 13% | ||
Number of fully used LUT-FF pairs | 2,377 | 4,431 | 53% | ||
Number of unique control sets | 210 | ||||
Number of slice register sites lost to control set restrictions |
847 | 11,440 | 7% | ||
Number of bonded IOBs | 7 | 102 | 6% | ||
Number of LOCed IOBs | 7 | 7 | 100% | ||
IOB Flip Flops | 2 | ||||
Number of RAMB16BWERs | 20 | 32 | 62% | ||
Number of RAMB8BWERs | 0 | 64 | 0% | ||
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% | ||
Number used as BUFIO2s | 1 | ||||
Number used as BUFIO2_2CLKs | 0 | ||||
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% | ||
Number of BUFG/BUFGMUXs | 3 | 16 | 18% | ||
Number used as BUFGs | 3 | ||||
Number used as BUFGMUX | 0 | ||||
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% | ||
Number of ILOGIC2/ISERDES2s | 1 | 200 | 1% | ||
Number used as ILOGIC2s | 1 | ||||
Number used as ISERDES2s | 0 | ||||
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% | ||
Number of OLOGIC2/OSERDES2s | 1 | 200 | 1% | ||
Number used as OLOGIC2s | 1 | ||||
Number used as OSERDES2s | 0 | ||||
Number of BSCANs | 2 | 4 | 50% | ||
Number of BUFHs | 0 | 128 | 0% | ||
Number of BUFPLLs | 0 | 8 | 0% | ||
Number of BUFPLL_MCBs | 0 | 4 | 0% | ||
Number of DSP48A1s | 3 | 16 | 18% | ||
Number of ICAPs | 0 | 1 | 0% | ||
Number of MCBs | 0 | 2 | 0% | ||
Number of PCILOGICSEs | 0 | 2 | 0% | ||
Number of PLL_ADVs | 1 | 2 | 50% | ||
Number of PMVs | 0 | 1 | 0% | ||
Number of STARTUPs | 0 | 1 | 0% | ||
Number of SUSPEND_SYNCs | 0 | 1 | 0% | ||
Number of RPM macros | 12 | ||||
Average Fanout of Non-Clock Nets | 4.04 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Translation Report | Current | 格 7 28 15:05:46 2016 | 0 | 16 Warnings (0 new) | 3 Infos (0 new) | |
Map Report | Current | 格 7 28 15:06:51 2016 | 0 | 35 Warnings (0 new) | 556 Infos (0 new) | |
Place and Route Report | Current | 格 7 28 15:07:30 2016 | 0 | 36 Warnings (0 new) | 0 | |
Post-PAR Static Timing Report | Current | 格 7 28 15:07:40 2016 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report | Current | 格 7 28 15:08:01 2016 | 0 | 35 Warnings (0 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | 格 7 28 15:08:01 2016 | |
WebTalk Log File | Current | 格 7 28 15:08:07 2016 |