Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) fbeefb39acb64915b57ff8bb34a676bf.8F733EBCE6594550923FCC5C023F7D92.4 Target Package: tqg144
Registration ID 211202240_0_0_713 Target Speed: -3
Date Generated 2016-06-22T17:04:17 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz CPU Speed 3502 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz CPU Speed 3502 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 32-bit up counter=1
Registers=3
  • Flip-Flops=3
MiscellaneousStatistics
  • AGG_BONDED_IO=34
  • AGG_IO=34
  • AGG_LOCED_IO=34
  • AGG_SLICE=11
  • NUM_BONDED_IOB=34
  • NUM_BSFULL=28
  • NUM_BSLUTONLY=4
  • NUM_BSREGONLY=3
  • NUM_BSUSED=35
  • NUM_BUFG=1
  • NUM_LOCED_IOB=34
  • NUM_LOGIC_O5ANDO6=1
  • NUM_LOGIC_O5ONLY=26
  • NUM_LOGIC_O6ONLY=4
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=26
  • NUM_SLICEL=7
  • NUM_SLICEX=4
  • NUM_SLICE_CARRY4=7
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=60
  • NUM_SLICE_FF=31
  • NUM_SLICE_UNUSEDCTRL=3
  • NUM_UNUSABLE_FF_BELS=9
NetStatistics
  • NumNets_Active=88
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=6
  • NumNodesOfType_Active_BUFGOUT=1
  • NumNodesOfType_Active_BUFHINP2OUT=2
  • NumNodesOfType_Active_CLKPIN=8
  • NumNodesOfType_Active_CLKPINFEED=2
  • NumNodesOfType_Active_DOUBLE=33
  • NumNodesOfType_Active_GENERIC=43
  • NumNodesOfType_Active_GLOBAL=13
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=31
  • NumNodesOfType_Active_IOBOUTPUT=31
  • NumNodesOfType_Active_LUTINPUT=32
  • NumNodesOfType_Active_OUTBOUND=57
  • NumNodesOfType_Active_OUTPUT=43
  • NumNodesOfType_Active_PADINPUT=20
  • NumNodesOfType_Active_PADOUTPUT=12
  • NumNodesOfType_Active_PINBOUNCE=10
  • NumNodesOfType_Active_PINFEED=61
  • NumNodesOfType_Active_QUAD=134
  • NumNodesOfType_Active_REGINPUT=3
  • NumNodesOfType_Active_SINGLE=37
SiteStatistics
  • BUFG-BUFGMUX=1
  • IOB-IOBM=17
  • IOB-IOBS=17
  • SLICEX-SLICEM=1
SiteSummary
  • BUFG=1
  • BUFG_BUFG=1
  • CARRY4=7
  • HARD0=1
  • INVERTER=1
  • IOB=34
  • IOB_IMUX=12
  • IOB_INBUF=12
  • IOB_OUTBUF=22
  • LUT5=27
  • LUT6=32
  • PAD=34
  • REG_SR=31
  • SLICEL=7
  • SLICEX=4
 
Configuration Data
IOB_OUTBUF
  • DRIVEATTRBOX=[12:22]
  • SLEW=[SLOW:22]
  • SUSPEND=[3STATE:22]
REG_SR
  • CK=[CK:28] [CK_INV:3]
  • LATCH_OR_FF=[FF:31]
  • SRINIT=[SRINIT0:31]
  • SYNC_ATTR=[ASYNC:31]
SLICEL
  • CLK=[CLK:7] [CLK_INV:0]
SLICEX
  • CLK=[CLK:0] [CLK_INV:1]
 
Pin Data
BUFG
  • I0=1
  • O=1
BUFG_BUFG
  • I0=1
  • O=1
CARRY4
  • CIN=6
  • CO3=6
  • CYINIT=1
  • DI0=7
  • DI1=7
  • DI2=7
  • DI3=6
  • O0=7
  • O1=7
  • O2=7
  • O3=7
  • S0=7
  • S1=7
  • S2=7
  • S3=7
HARD0
  • 0=1
INVERTER
  • IN=1
  • OUT=1
IOB
  • I=12
  • O=22
  • PAD=34
IOB_IMUX
  • I=11
  • I_B=1
  • OUT=12
IOB_INBUF
  • OUT=12
  • PAD=12
IOB_OUTBUF
  • IN=22
  • OUT=22
LUT5
  • O5=27
LUT6
  • A4=28
  • A6=31
  • O6=32
PAD
  • PAD=34
REG_SR
  • CK=31
  • D=31
  • Q=31
SLICEL
  • A4=7
  • A6=7
  • AQ=7
  • B4=7
  • B6=7
  • BQ=7
  • C4=7
  • C6=7
  • CIN=6
  • CLK=7
  • COUT=6
  • CQ=7
  • D4=7
  • D6=6
  • DQ=7
SLICEX
  • A=3
  • A6=3
  • AQ=1
  • AX=1
  • B=1
  • B6=1
  • BQ=1
  • BX=1
  • CLK=1
  • CQ=1
  • CX=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 19 19 0 0 0 0 0
bitgen 13 13 0 0 0 0 0
map 21 20 0 0 0 0 0
ngdbuild 22 22 0 0 0 0 0
par 20 20 0 0 0 0 0
trce 20 20 0 0 0 0 0
xst 19 19 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2016-06-22T13:29:00
PROP_intWbtProjectID=8F733EBCE6594550923FCC5C023F7D92 PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FD_1=3 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=11 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=27 NGDBUILD_NUM_MUXCY=27
NGDBUILD_NUM_OBUF=22 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=28
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=28 NGDBUILD_NUM_FD_1=3 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=11 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=6 NGDBUILD_NUM_LUT1=27
NGDBUILD_NUM_MUXCY=27 NGDBUILD_NUM_OBUF=22 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=28
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx9-3-tqg144
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5